After a microelectronic chip or die has been manufactured, it is typically packaged before it is sold. The package provides electrical connection to the chip's internal circuitry, protection from the external environment, and heat dissipation. In one package system, a chip is flip-chip connected to a package substrate. In a flip-chip package, also known as a controlled-collapse chip connection (C4), electrical leads on the die are distributed on its active surface and the active surface is electrically connected to corresponding leads on a package substrate.
FIGS. 1A through 1C illustrate a prior art method for flip-chip packaging a microelectronic chip or die. In FIG. 1A, a portion of a integrated circuit (IC) die 100 including a conductive metal bump 114 is illustrated. For clarity, the conductive metal bump will herein be referred to as a die-side bump. The IC die 100 includes a substrate 102, a device layer 104, an interconnect region 106, and an IC pad 108. The device layer 104 typically includes a variety of electrical circuit elements (not shown), such as transistors, conductors, and resistors, formed in and on a semiconductor substrate material. The interconnect region 106 includes layers of interconnected metal vias and metal lines, which are separated by dielectric materials, that provide electrical connection between the devices of the device layer 104 and electrical routing to conductive IC pads, including the IC pad 108. Typically, a dielectric layer 110, a barrier metal 112, and a die-side bump 114 are formed over the IC pad 108, with the die-side bump 114 providing a structure for electrical connection from the die 100 to an external package substrate.
As shown in FIGS. 1B and 1C, in a common C4 flip-chip package system, the IC die 100 is flip-chip bonded to a package substrate 116 such that its active surface, including its die-side bumps 114, faces a surface of the package substrate 116 that includes solder bumps 118. An electrical connection is formed between the die-side bumps 114 and the solder bumps 118 at a joint 120. As shown, the joint 120 typically includes a portion of the die-side bumps 114 being depressed into the solder bumps 118. Heat may be applied to reflow at least the solder material to create a fixed connection between the solder bumps 118 and the die-side bumps 114.
Also illustrated in FIG. 1C is an underfill material 122 that is provided between the IC die 100 and the package substrate 116. In some processes, the underfill material is a capillary underfill material and the die-side bumps 114 are copper. In such systems, the underfill material 122 may not adhere well to the die-side bumps 114 of the IC die 100. The lack of adhesion between the die-side bumps 114 and the underfill material 122 may cause numerous difficulties. For example, it may cause cracking of the dielectric material in the interconnect region 106 of the IC die 100, or in the dielectric layer 110, leading to device failure. Further, lack of adhesion may cause undesirable gaps and cracks in the underfill material 122 itself.
Attempts have been made to address the adhesion issue, however, currently there is no good solution to this problem. Modifications to the underfill material formulation have been researched but only minor improvements in underfill-to-die-side bump adhesion have been observed thus far. Roughening the sidewalls of the die-side bumps 114 using a wet chemical microetchant is another method of improving adhesion. Unfortunately, the wet chemical microetchant also roughens the top surface of the die-side bumps 114, leading to packaging issues such as entrapped flux that causes voids in the die-side bump-to-solder bump connection after the semiconductor chip is attached. The microetchant also tends to damage other films on the wafer, such as the buffer coating material. Accordingly, alternate methods of roughening the sidewalls of the die-side bumps 114 are needed.